`timer_interrupt_handler.ino`

Efinix Sapphire RV64 : Configurable 64-bit RISC-V SoC for FPGAs · File : timer_interrupt_handler.ino · Language : C (RISC-V) · Use case : Utiliser les interruptions du timer pour une tâche périodique sans bloquer le CPU.

Shows the use of hardware interrupts to improve energy efficiency and responsiveness.

Configure a Timer block with interrupt output in Efinity. Ensure the interrupt vector is correctly mapped in your startup code. The mstatus register must be configured to allow machine mode interrupts.

timer_interrupt_handler.ino

#include <stdint.h>

#define TIMER_BASE 0x80004000
#define TIMER_CTRL (*(volatile uint32_t *)(TIMER_BASE + 0x00))
#define TIMER_VAL  (*(volatile uint32_t *)(TIMER_BASE + 0x04))
#define TIMER_CMP  (*(volatile uint32_t *)(TIMER_BASE + 0x08))

// Adresse du vecteur d'interruption (à définir dans le linker script/startup)
extern void handle_timer_irq(void);

void setup_timer() {
    TIMER_CMP = 1000000; // 1ms @ 1GHz (ajuster selon fréquence)
    TIMER_CTRL = 0x01;   // Enable timer & interrupt
}

void handle_timer_irq() {
    // Effacer l'interruption
    TIMER_CTRL |= 0x02; 
    // Action périodique
    // Ex: Toggle GPIO
}

int main() {
    setup_timer();
    // Activer les interruptions globales (CSR mstatus)
    asm volatile("csrs mstatus, 8"); 
    
    while(1) {
        // Tâches principales non critiques
    }
    return 0;
}

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