`uart_echo_riscv.ino`

Efinix Sapphire RV64 : Configurable 64-bit RISC-V SoC for FPGAs · File : uart_echo_riscv.ino · Language : C (RISC-V) · Use case : Implémenter une boucle d'écho série (UART) pour le débogage interactif.

Enables verification of serial communication with the SoC, essential for debugging without JTAG.

Enable a UART block in Efinity. Use a serial terminal (115200 bauds) connected to the FPGA. This code assumes a standard APB or AXI-lite interface. Adjust status masks according to the Efinix IP datasheet.

uart_echo_riscv.ino

#include <stdint.h>

// Adresse de base UART (à adapter selon la config Efinity)
#define UART_BASE 0x80001000
#define UART_DATA (*(volatile uint8_t *)(UART_BASE + 0x00))
#define UART_STAT (*(volatile uint8_t *)(UART_BASE + 0x04))

#define RX_READY 0x01
#define TX_READY 0x02

void uart_putc(char c) {
    while (!(UART_STAT & TX_READY));
    UART_DATA = c;
}

int main() {
    char c;
    while (1) {
        if (UART_STAT & RX_READY) {
            c = UART_DATA;
            uart_putc(c); // Echo
        }
    }
    return 0;
}

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