⚖ Comparison : ESP8266 (ESP-12E module) vs GD32F103 (GigaDevice) — chip + Blue-Pill-compatible boards
Comparison of declared technical characteristics : ESP8266 (ESP-12E module) et GD32F103 (GigaDevice) — chip + Blue-Pill-compatible boards (17 characteristics). See the full board sheet : ESP8266 (ESP-12E module) · GD32F103 (GigaDevice) — chip + Blue-Pill-compatible boards.
| Characteristics | ESP8266 (ESP-12E module) | GD32F103 (GigaDevice) — chip + Blue-Pill-compatible boards |
|---|---|---|
soc_mcu | ESP8266EX, single-core Tensilica L106 (Diamond Standard 106Micro) 32-bit RISC, 80 MHz default, up to 160 MHz ( | — |
cpu | 1 core, ~80% of processing power left free for the user after the Wi-Fi RTOS stack (Espressif product page). No GPU. | — |
memory | 160 KB total RAM: 32 KB instruction RAM (iRAM), 32 KB instruction cache, 96 KB dRAM (80 KB usable for SDK+heap, 16 KB ROM-mapped) ( | — |
storage | external QSPI flash, 512 KB–4 MB typical, up to 16 MB supported; ESP-12E ships with 4 MB ( No filesystem in silicon — use SPIFFS/LittleFS on flash. | 16 KB to 3072 KB on-chip flash (family max 3 MB; Blue Pill parts 64/128 KB). Erase granularity is page-based: 1 KB pages on medium-density (MD) parts, 2 KB/4 KB pages on HD/XD/CL dual-bank parts ([GD32F10x User Manual §2.3.1]; the official SPL example uses #define FMC_PAGE_SIZE 0x400 = 1024 B (SPL V2.2.2 FMC example, mirror). Endurance 100 k cycles, data retention 20 y @125 °C, page erase 60–450 ms. |
connectivity | Wi-Fi 802.11 b/g/n 2.4 GHz only (no Bluetooth, no Ethernet). On-chip TR switch, balun, LNA, PA and matching network ( ESP-12E: PCB-trace antenna + external antenna footprint. | — |
gpio | 17 GPIOs on the chip; fewer exposed on boards. Peripherals: SPI, I2C (software/bit-banged only), I2S with DMA, UART (plus TX-only UART on GPIO2), 10-bit SAR ADC on a single pin (ADC0/A0) ( - GPIO6–GPIO11 are wired to the flash chip — never use them ( - GPIO16: no interrupt, no PWM, no I2C; used for deep-sleep wake (wired to RST). - PWM is software (R-WS2812/ESP8266WiFi-based analogWrite), 1 effective channel family via ESP8266PWM. | — |
logic_level | 3.3 V only, VCC up to 3.6 V; NOT 5 V tolerant ( | — |
power | 3.3 V DC, typically 3.0–3.6 V; deep-sleep mode in the tens of µA range, three power modes (active/sleep/deep-sleep) ( > | 2.6–3.6 V supply and I/O; VBAT 1.8–3.6 V. Run @108 MHz: typ 45.5 mA (all peripherals on) / 34 mA (off) on small parts; 66.3/41.2 mA on large parts; @72 MHz 30.7/45.0 mA. Standby ≈5.6–5.8 µA (RTC on); sleep wake-up 4.5 µs. |
tx_current_caveat | Wi-Fi transmit bursts can pull sharp current peaks; designs need a 3.3 V rail able to supply ≥ 300–500 mA peaks or brownout resets occur (widely documented; see the ESP8266 Arduino core docs, | — |
temperature | industrial range advertised by Espressif ("wide operating temperature range"); exact grade depends on module. > | −40 to +85 °C operating ("Industrial" grade ordering codes), storage −55 to +150 °C, TJ max 125 °C. |
mcu_cpu | — | Arm Cortex-M3, 32-bit, up to 108 MHz with zero-wait-state flash accesses (vs 72 MHz on the ST STM32F103 — see Features). Zero-wait applies to the first 256 KB of flash only (GD32F10x User Manual EN V2.3 §2.1, mirror). |
gpu | — | none (MCU). |
ram | — | 6/10/20 KB SRAM on 16–128 KB parts (T/C/R/V 4/6/8/B); 48–96 KB on 256 KB–3 MB parts. Family max: 96 KB. |
connectivity_radios | — | none integrated (no WiFi/BT/Ethernet on GD32F103; Ethernet MAC exists only on the GD32F107 sibling gd32mcu.com Cortex-M3 page). Wired: 1× USB 2.0 FS device (48 MHz clock derived from main PLL, HSE crystal required — datasheet §3.17), 1× CAN 2.0B, up to 3× SPI, 2× I2C, 3× USART + 2× UART, 2× I2S (8–192 kHz), SDIO. |
gpio_analog | — | 26 GPIO (LQFP48) up to 112 (LQFP144), 5 V-tolerant I/O; up to 3× 12-bit SAR ADC @ 1 MSPS (ADC2 absent on C4/6/8/B), 16–21 channels, internal temperature sensor (ADC_IN16); 2× 12-bit DAC on C/D/E and larger parts; DMA0 7-ch + DMA1 5-ch; up to 10 general 16-bit timers + 2 advanced + 2 basic; RTC; EXMC external memory controller on LQFP100/144 parts. |
clocking | — | factory-trimmed internal IRC8M (±1 % @25 °C), HXTAL 4–16 MHz, PLL ×2–32, IRC40K + LXTAL 32.768 kHz for RTC/FWDGT. APB1 max 54 MHz, APB2 max 108 MHz, ADC clock ≤14 MHz. |
boot | — | BOOT0 pins select main flash / system memory bootloader / SRAM; the system bootloader sits at 0x1FFF B000–0x1FFF F7FF and option bytes at 0x1FFF F800 (datasheet memory map) — note this differs from the STM32F103 system-memory layout. A 96-bit unique device ID and memory-density signature exist (User Manual §1.5.2 "Unique device ID (96 bits)"); > |
ESP8266 (ESP-12E module) GD32F103 (GigaDevice) — chip + Blue-Pill-compatible boards