🛠 Drive a BLDC motor with synchronized PWM/ADC on HPM5100

Objectives

This tutorial explains how to leverage the HPM5100's motor control capabilities to drive a Brushless DC (BLDC) motor. The goal is to understand the hardware synchronization between PWM signals and ADC sampling, which is essential for Field-Oriented Control (FOC) or six-step driving. We will use the 32 PWM channels and 4 SAR 16-bit ADCs clocked at 2 MSPS to minimize latency and maximize torque accuracy.

Required Materials

• HPM5100 Development Board (HPM5151)
• Suitable BLDC power kit (3 half-bridges)
• Current and voltage probes (or integrated shunts)
• JTAG/SWD programming cables
• PC with HPM SDK v1.13.0 installed

Steps

1. SDK Configuration : Ensure the environment variable points to HPM SDK v1.13.0. Open a terminal and navigate to the basic motor control example.

cd hpm_sdk/samples/drivers/motor_control/basic

1. PWM Timer Initialization : The HPM5100 has synchronized timers. Configure a main timer (e.g., TMR1) to generate the 6 complementary PWM signals required for the three-phase bridge. The frequency should be high (e.g., 20 kHz) to reduce losses.

pwm_init_config_t config = {
    .clk_src = pwm_clk_src_axi,
    .pwm_freq = 20000,
    .pwm_sync_src = pwm_sync_src_none,
    .pwm_sync_out_en = false,
    .pwm_sync_in_en = false,
};
pwm_init(HPM_PWM1, &config);

1. SAR ADC Setup : Select two ADCs for phases U and V. The third current is derived. Configure a hardware trigger linked to the PWM period center to sample at the optimal moment (when currents are stable).

adc_init_config_t adc_cfg = {
    .clk_src = adc_clk_src_ahb,
    .sample_res = adc_sample_res_16bit,
    .trigger_src = adc_trig_src_hw,
};
adc_init(HPM_ADC1, &adc_cfg);

1. PWM-ADC Trigger Linking : Link the PWM1 synchronization signal to the ADC hardware trigger. This ensures each ADC conversion starts exactly in the middle of the active PWM window, avoiding switching noise peaks.

pwm_set_sync_in_source(HPM_PWM1, 0, pwm_sync_src_tmr1_sync_out);
adc_set_trigger_source(HPM_ADC1, ADC_TRIG_PWM1_SYNC_OUT);

1. Control Loop : Implement a simple control loop that reads ADC values, calculates the error relative to the setpoint, and adjusts the PWM duty cycle via registers. Use DMA to transfer ADC data to SRAM without CPU intervention.

Verification

Use an oscilloscope to verify that ADC trigger edges coincide with the center of PWM pulses. Ensure motor output waveforms are clean and symmetrical. Check for ADC saturation during current peaks.

Further Reading

Explore using the 4 integrated PGA op-amps to amplify shunt current signals before the ADC, improving effective resolution without external noise. Also test hot-startup sequences with specific pre-charge routines.