⚖ Comparatif : ESP32-H2 vs ESP32-S2
Comparatif des caractéristiques techniques déclarées : ESP32-H2 et ESP32-S2 (11 caractéristiques). Voir la fiche complète : ESP32-H2 · ESP32-S2.
| Caractéristiques | ESP32-H2 | ESP32-S2 |
|---|---|---|
cpu | single-core 32-bit ESP-RISC-V, four-stage pipeline, up to 96 MHz; 303.38 CoreMark at 96 MHz (3.16 CoreMark/MHz); 40 nm process (datasheet §4.1.1.1: process node: | single-core Tensilica Xtensa LX7 @ up to 240 MHz (160 MHz default in many configs); no GPU ( ESP32-S2 datasheet URL above). |
gpu | none (embedded MCU). | — |
memory | 320 KB SRAM, 128 KB ROM, 4 KB LP SRAM (retained in deep-sleep), 16 KB cache (product page + datasheet §4.1.2). | 320 KB internal SRAM, ~1.5 KB low-power SRAM, 448 KB ROM; external SPI flash up to 16 MB (4/8 MB typical); optional quad PSRAM (module-dependent) (ESP32-S2 datasheet: |
storage | 2 MB or 4 MB SiP in-package flash; SPI/Dual/Quad/QPI interface supports up to 16 MB off-package flash (datasheet §1.2, §4.1.2.2). No PSRAM. | — |
connectivity | one 2.4 GHz radio combining IEEE 802.15.4 (Thread, Zigbee, Matter over Thread; 250 Kbps OQPSK PHY, RX sensitivity up to −102.5 dBm) and Bluetooth 5 (LE) incl. Coded PHY/Long Range 125 & 500 Kbps (RX sensitivity up to −106.5 dBm) and Bluetooth Mesh; TX power −24 to +20 dBm (datasheet §1.2/§5; product page). No Wi-Fi, no Bluetooth Classic — that is the key difference vs ESP32-C6, which adds Wi-Fi 6 ( | Wi-Fi 802.11 b/g/n 2.4 GHz (HT40, ESP-WIFI-MESH). No Bluetooth at all — a defining cut vs the ESP32 ( |
usb | USB 2.0 Full-Speed (12 Mbps) USB-Serial/JTAG controller on GPIO26/27 (D−/D+) — device console + flashing + JTAG debug, not OTG (datasheet §1.2, §4.2.1.6; DevKitM-1 guide: | native USB-OTG (device + host) on GPIO19 (D−)/GPIO20 (D+) — flash/debug over USB without any bridge chip; basis of the QT-Py form factor ( |
gpio | 19 programmable GPIOs; digital pins GPIO0–GPIO5 and GPIO22–GPIO27 are NOT usable in deep-sleep (LP-domain pins only); GPIO26/27 default to USB function with internal pull-up; default drive strength 20 mA (40 mA on GPIO26/27) (datasheet §2.2–2.3). - Peripherals: 2× UART, 1× general-purpose SPI (plus 2 dedicated flash SPI ports), 2× I2C, 1× I2S, RMT (2 TX + 2 RX channels), LED PWM (6 channels), TWAI (CAN 2.0A), GDMA (3 TX + 3 RX channels), SoC event task matrix (ETM) (datasheet §1.2). - ADC: 12-bit SAR, up to 5 channels; plus temperature sensor and analog (PAD voltage) comparator; no DAC in the datasheet peripheral set (datasheet §1.2, §4.2.2). | 43 programmable GPIOs, freely matrix-routed to USB-OTG, LCD (8080/SPI), 8-bit parallel camera interface, SPI, I2S, UART, ADC, DAC, touch (14 capacitive-touch GPIOs) ( - ADC: 12-bit SAR, up to 20 channels (ADC1 GPIO1–14 + ADC2); ADC2 blocked while Wi-Fi runs (datasheet URL above). - DAC: one 8-bit channel (GPIO17) (datasheet URL above). - LEDC PWM, RMT, motor-control PWM, SDIO master (datasheet URL above). |
logic_level | 3.3 v | 3.3 v |
power | VDD3P3 (3.0–3.6 V abs-max 3.6 V) + VBAT pin (battery domain, shared with GPIO12/XTAL_32K functions); CHIP_EN must not float (datasheet §2.5, §5.1). | deep sleep in the single-digit µA class with RTC wake; multiple low-power modes (datasheet URL above). > |
consumption_3_3_v_25_c_datasheet_table_5_6_5_9 | TX 36 mA @ 0 dBm / 140 mA @ +20 dBm; RX 24–25 mA; modem-sleep 3–17 mA typ; light-sleep 25–85 µA typ; deep-sleep 7 µA typ; power-off 1 µA. | — |
temperature | −40 to +105 °C recommended ambient (FH-S parts); HTOL qualified 125 °C/1000 h (datasheet Table 1-1, §5.6). | −40 °C to +105 °C ( |