ESP32-C3
⚡ The essentials in 60 seconds
- cpu — single-core 32-bit RISC-V RV32IMC @ up to 160 MHz, plus a 20 MHz ultra-low-power RISC-V coprocessor ("power management" core) ( datasheet
- memory — 400 KB internal SRAM, 384 KB ROM, 24 KB in low-power SRAM ( datasheet URL above).
- storage — external or in-package SPI flash, 4 MB typical on MINI-1 (up to 16 MB supported) (
- connectivity — Wi-Fi 802.11 b/g/n 2.4 GHz + Bluetooth 5 (LE) with long-range (Coded PHY), BLE Mesh, ESP-WIFI-MESH; no Bluetooth Classic (
- usb — USB-Serial/JTAG device peripheral (CDC console + flashing + JTAG debug on GPIO18/19) — it is not USB-OTG; you cannot build USB HID devices with it (datasheet URL above).
- gpio — 22 programmable GPIOs (GPIO0–GPIO21); 2× UART, 1× I2C, 1× SPI, 2× I2S, 1× RMT TX/RX pair, LEDC PWM (6 channels), 1× TWAI (CAN), GPIO matrix routing (datasheet URL above). - ADC: 12-bit SAR with a handful of channels on GPIO0–GPIO5 (exact mapping package-dependent). >
- On this board : 9 tutorials · 10 code
The ESP32-C3, manufactured by Espressif Systems, represents a significant shift in the landscape of affordable microcontrollers, serving as the company’s first system-on-chip to adopt the RISC-V instruction set architecture. Announced in 2020 and entering volume production between 2021 and 2022, this chip was designed with a clear strategic goal: to provide a cost-effective successor to the widely popular ESP8266 while integrating modern wireless standards. It acts as the entry point for the broader ESP32 family, offering a balance of performance, connectivity, and security that appeals to hobbyists and industrial developers alike. The chip is available in various configurations, including versions with in-package flash memory ranging from 2 MB to 16 MB, as well as no-flash variants for designs that require external storage. Common implementations include the ESP32-C3-MINI-1 and ESP32-C3-WROOM-02 modules, which are often found on development boards such as the official DevKitM-1, the compact Seeed XIAO ESP32C3, and the ubiquitous "SuperMini" clones. While the chip itself has been marketed at approximately two US dollars in volume, with modules and boards often costing under three dollars, precise official retail prices remain unverified.
At the heart of the ESP32-C3 is a single-core, 32-bit RISC-V processor running at speeds up to 160 MHz. For those unfamiliar with the term, RISC-V is an open standard instruction set architecture, meaning it is not licensed by a single proprietary vendor, which contributes to the chip's low cost. Alongside the main core, the chip features a dedicated 20 MHz ultra-low-power RISC-V coprocessor specifically designed for power management tasks. This dual-core approach allows the main processor to sleep deeply while the coprocessor handles basic wake-up events, significantly extending battery life in portable applications. The system includes 400 KB of internal SRAM, 384 KB of ROM, and 24 KB of low-power SRAM. Storage is handled via SPI flash, either integrated within the package or external, with 4 MB being typical for the MINI-1 module. The chip operates at a logic level of 3.3 volts and is not tolerant of 5-volt signals, a critical consideration for beginners connecting sensors or peripherals.
Connectivity is one of the ESP32-C3’s strongest selling points. It supports Wi-Fi 802.11 b/g/n on the 2.4 GHz band and Bluetooth 5 Low Energy (LE). The inclusion of Bluetooth 5 is notable because it introduces features like long-range communication via Coded PHY and BLE Mesh networking, capabilities that were previously reserved for more expensive chips. However, it is crucial to understand that the ESP32-C3 does not support Bluetooth Classic, limiting its use in applications requiring legacy Bluetooth audio or file transfer profiles. Furthermore, the chip does not include an 802.15.4 radio, which is the standard used by Zigbee and Thread protocols. Consequently, the ESP32-C3 cannot function as a standalone Zigbee or Thread end-device; it can only serve as a Wi-Fi gateway host that communicates with an external 802.15.4 radio, such as the ESP32-H2. This distinction is vital for developers planning smart home projects, as choosing the C3 for a direct Zigbee sensor role would be a design error.
The input and output capabilities of the ESP32-C3 are modest but sufficient for many embedded tasks. The chip provides 22 programmable GPIOs, which are general-purpose input/output pins that can be configured for digital or analog functions. These pins support two UARTs for serial communication, one I2C bus, one SPI bus, and two I2S interfaces for audio. It also includes an LEDC PWM module with six channels for controlling brightness or motor speed, and a TWAI interface, which is Espressif’s implementation of the CAN bus protocol used in automotive and industrial applications. The GPIO matrix allows for flexible routing of signals, meaning most peripherals can be mapped to most pins, though some restrictions apply. For instance, GPIOs 11 through 17 may be restricted on modules with in-package flash, and GPIOs 9 and 10 can conflict with SPI flash on certain chip variants. The analog-to-digital converter (ADC) is 12-bit and available on a handful of channels, but it lacks a digital-to-analog converter (DAC). Additionally, the ADC shares resources with the Wi-Fi radio, which can introduce noise into readings while Wi-Fi is transmitting, necessitating software averaging or reading during modem sleep windows for accurate data.
A key feature of the ESP32-C3 is its built-in USB-Serial/JTAG peripheral. Unlike previous ESP32 chips that required an external USB-to-serial converter chip (like the CP2102) for programming, the C3 can be flashed and debugged directly over a USB-C connection. This peripheral provides a CDC console for serial communication and JTAG for hardware debugging. However, it is important to clarify that this is not a USB On-The-Go (OTG) interface. This means the ESP32-C3 cannot act as a USB host or create USB HID devices such as keyboards or mice. Developers porting code from the ESP32-S2 or S3, which do support USB OTG, will find that their USB device examples will not work on the C3. The USB interface is strictly for development and communication with a host computer, not for emulating USB peripherals.
Security is another area where the ESP32-C3 stands out for a low-cost chip. It includes hardware-accelerated cryptographic features, including RSA-3072 secure boot, AES-128 and AES-256-XTS flash encryption, and digital signature and HMAC peripherals. These features allow developers to create products that are resistant to firmware tampering and cloning, which is increasingly important for commercial IoT devices. The chip also supports multiple low-power modes, with deep sleep currents in the single-digit microampere range, although exact figures vary by mode and are not fully verified in all public documentation. The temperature range is marketed for industrial and lighting applications, with specific grades determined by the chip marking.
Software support for the ESP32-C3 is extensive. The official SDK is ESP-IDF, Espressif’s comprehensive development framework. For hobbyists, the Arduino core for ESP32 supports the C3, allowing the use of the familiar Arduino programming model. However, because the C3 uses RISC-V rather than the Xtensa architecture used in older ESP32 chips, Arduino libraries that rely on Xtensa-specific assembly code will not work. MicroPython, Rust (via esp-rs), Zephyr, Tasmota, and ESPHome all provide official support for C3 boards. Programming is typically done via the built-in USB interface or UART0, using tools like idf.py or esptool. The boot process involves specific "strapping pins" (GPIO2, GPIO8, and GPIO9) that determine the boot mode. For example, GPIO9 is commonly used as the BOOT button, and GPIO8 must be high at boot to avoid entering download mode. Incorrect handling of these pins is a common source of confusion, often resulting in boards that appear dead or fail to flash.
Finally, potential users should be aware of quality variations in third-party boards, particularly the numerous "SuperMini" clones. These boards often lack documented flash sizes, missing auto-reset circuitry (requiring manual button presses to flash), and use weak voltage regulators that can cause brownout loops during Wi-Fi transmission bursts. While the ESP32-C3 itself is a robust and capable chip, the experience can vary significantly depending on the specific board chosen. It is a powerful tool for Wi-Fi and Bluetooth Low Energy applications, offering modern security and connectivity at a very low price point, provided the developer understands its architectural limitations regarding USB, radio protocols, and pin constraints.
Pinout diagram
| Attr | Specs | verified |
|---|---|---|
cpu | single-core 32-bit RISC-V RV32IMC @ up to 160 MHz, plus a 20 MHz ultra-low-power RISC-V coprocessor ("power management" core) ( datasheet | ✔ |
memory | 400 KB internal SRAM, 384 KB ROM, 24 KB in low-power SRAM ( datasheet URL above). | ✔ |
storage | external or in-package SPI flash, 4 MB typical on MINI-1 (up to 16 MB supported) ( | ✔ |
connectivity | Wi-Fi 802.11 b/g/n 2.4 GHz + Bluetooth 5 (LE) with long-range (Coded PHY), BLE Mesh, ESP-WIFI-MESH; no Bluetooth Classic ( | ✔ |
usb | USB-Serial/JTAG device peripheral (CDC console + flashing + JTAG debug on GPIO18/19) — it is not USB-OTG; you cannot build USB HID devices with it (datasheet URL above). | ? unverified |
gpio | 22 programmable GPIOs (GPIO0–GPIO21); 2× UART, 1× I2C, 1× SPI, 2× I2S, 1× RMT TX/RX pair, LEDC PWM (6 channels), 1× TWAI (CAN), GPIO matrix routing (datasheet URL above). - ADC: 12-bit SAR with a handful of channels on GPIO0–GPIO5 (exact mapping package-dependent). > | ? unverified |
logic_level | 3.3 v | ? unverified |
power | multiple low-power modes with ULP FSM; deep sleep in the single-digit µA class (datasheet power tables). > | ? unverified |
temperature | high-temperature support marketed for industrial/lighting ( exact grade per chip marking — datasheet §General Characteristics. | ✔ |
- Manufacturer: Espressif Systems (Shanghai) (
- Year: announced 2020 (Espressif's first RISC-V Wi-Fi SoC), volume production 2021–2022. >
- Status: Active — Espressif's cost-reduction successor to the ESP8266 and entry point of the ESP32 family.
- Launch price: chip ≈ US$2 in volume per Espressif's launch messaging; C3 modules ≈ US$1.5–3, "SuperMini" boards often under US$3. >
- Variants: ESP32-SO3 (in-package flash) / ESP32-C3 chip suffixes encode flash (2/4/8/16 MB, e.g. ESP32-C3-MINI-1 modules with 4 MB); no-flash versions for external SPI flash designs (
- Modules: ESP32-C3-MINI-1/-1U ( ESP32-C3-WROOM-02/-02U.
- Common boards: ESP32-C3-DevKitM-1, ESP32-C3-DevKitC-0, ESP32-C3-DevKitM-2U, countless "ESP32-C3 SuperMini" clones, Seeed XIAO ESP32C3, Adafruit QT Py ESP32-C3.
＋ Strengths
- RISC-V core — Espressif's open-architecture, lowest-cost Wi-Fi+BLE5 SoC; balance of power/I-O/security pitched at ESP8266 replacement (
- BLE 5 long-range + Mesh on a sub-$2 chip (
- USB-Serial/JTAG built in: single USB-C port gives console, flashing and GDB — no CP2102 on SuperMini boards (datasheet URL above).
- Hardware crypto: RSA-3072 secure boot, AES-XTS, digital signature, HMAC (
- No 802.15.4 radio — the C3 is Wi-Fi + BLE 5 only. Espressif's product page lists no 802.15.4, and ESP-IDF soc_caps.h defines SOC_IEEE802154_SUPPORTED for ESP32-C6/H2 but not for C3 (verified 2026-10-13: Zigbee/Thread end devices need an ESP32-C6/H2; the C3 only appears as the Wi-Fi gateway host ( _[Corrected 2026-10-13: an earlier revision of this card wrongly credited the C3 with an 802.15.4 radio.]_
− Weaknesses
- Strapping pins GPIO2, GPIO8, GPIO9: GPIO8 must be HIGH at boot (else download mode), GPIO9 is the common BOOT button, GPIO2 must float/HIGH for SPI-boot; wrong levels = "port opens but won't flash/boot" (datasheet §Strapping Pins:
- USB is Serial/JTAG only: no OTG/HID — projects copied from S2/S3 USB examples fail conceptually (datasheet URL above).
- Only 22 GPIOs, 1 I2C, 1 SPI, 2 UARTs: pin planning is tight; GPIO11–17 may be restricted on modules with in-package flash (MINI-1 datasheet:
- GPIO9/GPIO10 vs SPI flash on some chip variants — check your exact part marking before using them (MINI-1 datasheet URL above).
- No DAC, no classic Bluetooth, single core: ports from ESP32 code that assumed those features need rework (product page comparison:
- ADC2-like Wi-Fi contention: ADC channels shared with RF path give noisy readings while Wi-Fi transmits; average or read in modem-sleep windows (ESP-IDF ADC guide:
- SuperMini clone quality: undocumented flash sizes, missing auto-reset circuitry (manual BOOT+RESET dance), and 3.3 V LDOs too weak for TX bursts — brownout loops are the #1 forum complaint (community:
- Retour d'expérience expert expert — expert-microcontroleur
- Je viens de finir un projet avec la ESP32-C3 et il faut être clair sur ses limites. Le RISC-V à 160 MHz est réactif et le BLE 5 avec Coded PHY est top, mais attention au USB : ce n'est pas de l'OTG. J'ai perdu du temps à vouloir faire un périphérique HID, c'est impossible, c'est juste du Serial/JTA… — expert-microcontroleur
- Merci pour le rappel sur le GPIO8, j'ai galéré pendant deux heures avec une SuperMini qui ne flashait plus. J'ai finalement compris que mon capteur branché dessus tirait la ligne vers le bas. Par contre, tu as testé l'ADC pendant que le Wi-Fi est actif ? J'ai des valeurs qui sautent dans tous les s… — maker_bricoleur
- Pour l'ADC, c'est un souci connu car les canaux partagent le chemin RF. Il faut soit faire des moyennes, soit mettre le modem en sommeil pendant la lecture via l'API ESP-IDF. Concernant les clones, je confirme les brownouts si le LDO est faible. J'ai dû ajouter un condensateur de 100uF en entrée po… — codemine
Community feedback and projects
- ESP32-C3 super mini deepsleep doorsensor forum.arduino.cc
- ESP32-C3 hangs randomly in light sleep forum.arduino.cc
- Correct pinout of the ESP32 C3 Supermini OLED electronics.stackexchange.com
- Getting App Inventor to work with BLE and Seeeduino ESP32C3 community.appinventor.mit.edu
- esp32-c3_datasheet_en.pdf datasheet
- esp32-c3-mini-1_datasheet_en.pdf datasheet
- Strapping pins GPIO2, GPIO8, GPIO9: GPIO8 must be HIGH at boot (else download mode), GPIO9 is the common BOOT button, GPIO2 must float/HIGH for SPI-boot; wrong levels = "port opens but won't flash/boot" (datasheet §Strapping Pins:
- USB is Serial/JTAG only: no OTG/HID — projects copied from S2/S3 USB examples fail conceptually (datasheet URL above).
- Only 22 GPIOs, 1 I2C, 1 SPI, 2 UARTs: pin planning is tight; GPIO11–17 may be restricted on modules with in-package flash (MINI-1 datasheet:
- GPIO9/GPIO10 vs SPI flash on some chip variants — check your exact part marking before using them (MINI-1 datasheet URL above).
- No DAC, no classic Bluetooth, single core: ports from ESP32 code that assumed those features need rework (product page comparison:
- ADC2-like Wi-Fi contention: ADC channels shared with RF path give noisy readings while Wi-Fi transmits; average or read in modem-sleep windows (ESP-IDF ADC guide:
- SuperMini clone quality: undocumented flash sizes, missing auto-reset circuitry (manual BOOT+RESET dance), and 3.3 V LDOs too weak for TX bursts — brownout loops are the #1 forum complaint (community:
- Faire clignoter la LED RGB sur GPIO8 debutant Schéma : IMG-esp32-c3-debutant-1-rgb-led-gpio8-blink.svg — Carte ESP32-C3 compacte avec LED RGB sur GPIO8 clignotant, broche signalée comme strapping
- Lire le bouton BOOT sur GPIO9 debutant Schéma : IMG-esp32-c3-debutant-2-bouton-boot-gpio9.svg — Bouton BOOT du ESP32-C3 câblé entre GPIO9 et GND avec résistance de pull-up interne, compteur d'appuis en console
- Console sur l'USB-C natif (USB-Serial/JTAG) debutant Schéma : IMG-esp32-c3-debutant-3-console-usb-c-serial-jtag.svg — Câble USB-C branché directement sur le ESP32-C3, périphérique USB-Serial/JTAG reliant terminal série et débogueur
- Bandeau NeoPixel piloté par le périphérique RMT intermediaire Schéma : IMG-esp32-c3-intermediaire-1-neopixel-rmt-gpio.svg — Bandeau de 8 LED WS2812 alimenté en 5 V, données sur GPIO7 du ESP32-C3 via le périphérique RMT, masses communes reliées
- Deep sleep et réveil RTC sur GPIO0 intermediaire Schéma : IMG-esp32-c3-intermediaire-2-deep-sleep-rtc-gpio0.svg — ESP32-C3 en deep sleep, bouton relié à GPIO0 (domaine RTC) réveillant la puce, consommation en microampères
- Publicité BLE 5 en longue portée (Coded PHY) intermediaire Schéma : IMG-esp32-c3-intermediaire-3-ble5-advertise-long-range.svg — ESP32-C3 émettant une publicité BLE 5 sur PHY codé 125 kbit/s, ondes de portée doublée vers un smartphone
- Wi-Fi + BLE 5 : mesurer la coexistence avance Schéma : IMG-esp32-c3-avance-1-wifi-ble5-coexistence.svg — ESP32-C3 mono-cœur avec radio unique 2,4 GHz, calendrier entrelaçant trames Wi-Fi et événements BLE
- Strapping GPIO2/8/9 : le diagnostic de boot avance Schéma : IMG-esp32-c3-avance-2-strapping-gpio2-8-9-boot.svg — Broches de strapping GPIO2, GPIO8 et GPIO9 du ESP32-C3 échantillonnées au reset, niveaux attendus indiqués
- ADC et bruit Wi-Fi : le moyennage qui sauve avance Schéma : IMG-esp32-c3-avance-3-adc-bruit-wifi-moyennage.svg — Lecture ADC sur ESP32-C3 avec et sans trafic Wi-Fi, bruit atténué par une moyenne sur 64 échantillons
Code library — examples written for this board
clignotante.inoArduinobouton-led.inoArduinorespiration.inoArduinodht22.inoArduinooled-i2c.inoArduinoserveur-web.inoArduinoble-compteur.inoArduinoservo.inoArduinosommeil-profond.inoArduinomesures.pyMicroPython
Examples and repos found online
- espressif/esp-idf github.com
- espressif/arduino-esp32 github.com
- espressif/esp-matter github.com