⚖ Comparison : ESP32-C6 vs ESP32-H2
Comparison of declared technical characteristics : ESP32-C6 et ESP32-H2 (18 characteristics). See the full board sheet : ESP32-C6 · ESP32-H2.
| Characteristics | ESP32-C6 | ESP32-H2 |
|---|---|---|
main_cpu | single 32-bit RISC-V HP core, RV32IMAC, four-stage pipeline, up to 160 MHz; CoreMark 496.66 (3.10 CoreMark/MHz at 160 MHz) (datasheet Product Overview: | — |
co_processor | low-power (LP) 32-bit RISC-V core, RV32IMAC, two-stage pipeline, up to 20 MHz; stays powered in deep-sleep (datasheet §LP RISC-V). Programmable via esp-lp-hal ( | — |
gpu | none. | none (embedded MCU). |
memory | 512 KB HP SRAM, 16 KB LP SRAM, 320 KB ROM, 32 KB L1 cache, 4096-bit eFuse (≤1792 bits user) (datasheet Feature List). | 320 KB SRAM, 128 KB ROM, 4 KB LP SRAM (retained in deep-sleep), 16 KB cache (product page + datasheet §4.1.2). |
storage | no in-package flash on the base ESP32-C6 (external SPI/QSPI flash via SPI0/1); FH4/FH8 have 4/8 MB in-package; modules ship 4–16 MB. No PSRAM interface listed in the C6 datasheet (the C61 derivative adds PSRAM per CNX above). | 2 MB or 4 MB SiP in-package flash; SPI/Dual/Quad/QPI interface supports up to 16 MB off-package flash (datasheet §1.2, §4.1.2.2). No PSRAM. |
wi_fi | 2.4 GHz only (2412–2484 MHz), 1T1R. Wi-Fi 6 (802.11ax) HE20 mode, up to 150 Mbps PHY, uplink+downlink OFDMA, downlink MU-MIMO, Target Wake Time (TWT) requester; backward 802.11b/g/n with 20/40 MHz bandwidth, MCS0–7; TX power up to +19.5 dBm (ax) (datasheet Wi-Fi Feature List; product page). | — |
bluetooth | Bluetooth 5 (LE) only — no Bluetooth Classic; Coded PHY long range, advertising extensions, 2 Mbps PHY; RX sensitivity down to −106 dBm @125 kbps (datasheet; product page). | — |
802_15_4 | IEEE 802.15.4 radio for Zigbee 3.0 and Thread 1.3; Wi-Fi/BLE/802.15.4 coexist and share one antenna (datasheet Product Overview). | — |
usb | USB 2.0 full speed (12 Mbit/s) via the USB Serial/JTAG controller on GPIO12/13 — CDC console + flashing + JTAG debug. It is a device-side debug/console interface, not USB-OTG (see Problems) (datasheet Feature List; TRM has a single USB chapter, "Chapter 32 USB Serial/JTAG Controller": | USB 2.0 Full-Speed (12 Mbps) USB-Serial/JTAG controller on GPIO26/27 (D−/D+) — device console + flashing + JTAG debug, not OTG (datasheet §1.2, §4.2.1.6; DevKitM-1 guide: |
gpio | 30 GPIOs on QFN40, 22 on QFN32; 5 strapping GPIOs; 6 GPIOs consumed when the flash is off-package (GPIO24/25/26/28/29/30 recommended for SPI0/1 flash) (datasheet §2.3.4). Strapping pins: GPIO5, GPIO8, GPIO9, GPIO15; boot-mode straps are GPIO8+GPIO9 (datasheet §3). GPIO12/13 = USB, GPIO4–7 = JTAG, GPIO16/17 = UART0, GPIO27 = VDD_SPI (datasheet §2.3.4 notes). | 19 programmable GPIOs; digital pins GPIO0–GPIO5 and GPIO22–GPIO27 are NOT usable in deep-sleep (LP-domain pins only); GPIO26/27 default to USB function with internal pull-up; default drive strength 20 mA (40 mA on GPIO26/27) (datasheet §2.2–2.3). - Peripherals: 2× UART, 1× general-purpose SPI (plus 2 dedicated flash SPI ports), 2× I2C, 1× I2S, RMT (2 TX + 2 RX channels), LED PWM (6 channels), TWAI (CAN 2.0A), GDMA (3 TX + 3 RX channels), SoC event task matrix (ETM) (datasheet §1.2). - ADC: 12-bit SAR, up to 5 channels; plus temperature sensor and analog (PAD voltage) comparator; no DAC in the datasheet peripheral set (datasheet §1.2, §4.2.2). |
logic_level | 3.0–3.6 V (VDDPST/VDD_SPI recommended 3.3 V); not 5 V tolerant (datasheet §2.5 Power Supply). | 3.3 v |
peripherals | 2× UART + LP UART, 2× I2C (1 HP + 1 LP), general-purpose SPI (plus 2 flash ports), 1× I2S, LED PWM 6 channels, MCPWM (motor), 2× TWAI® (CAN 2.0), RMT TX/RX, PARLIO, PCNT, SDIO slave, USB Serial/JTAG, event task matrix (ETM), GDMA, 52-bit system timer, 2× 54-bit general-purpose timers, watchdogs, RISC-V trace encoder (datasheet Feature List; ESP-IDF soc_caps: | — |
analog | 12-bit SAR ADC, up to 7 channels; on-chip temperature sensor; no DAC and no Hall sensor listed (datasheet §4.2.2 Analog Signal Processing). | — |
power | four modes (Active / Modem-sleep / Light-sleep / Deep-sleep); Deep-sleep ≈ 7 µA with LP SRAM retained (datasheet Power Management); 40 nm process (ESP-IDF Get Started: | VDD3P3 (3.0–3.6 V abs-max 3.6 V) + VBAT pin (battery domain, shared with GPIO12/XTAL_32K functions); CHIP_EN must not float (datasheet §2.5, §5.1). |
temperature | −40 ∼ 105 °C ambient, all orderable variants (datasheet Table 1-1). | −40 to +105 °C recommended ambient (FH-S parts); HTOL qualified 125 °C/1000 h (datasheet Table 1-1, §5.6). |
cpu | — | single-core 32-bit ESP-RISC-V, four-stage pipeline, up to 96 MHz; 303.38 CoreMark at 96 MHz (3.16 CoreMark/MHz); 40 nm process (datasheet §4.1.1.1: process node: |
connectivity | — | one 2.4 GHz radio combining IEEE 802.15.4 (Thread, Zigbee, Matter over Thread; 250 Kbps OQPSK PHY, RX sensitivity up to −102.5 dBm) and Bluetooth 5 (LE) incl. Coded PHY/Long Range 125 & 500 Kbps (RX sensitivity up to −106.5 dBm) and Bluetooth Mesh; TX power −24 to +20 dBm (datasheet §1.2/§5; product page). No Wi-Fi, no Bluetooth Classic — that is the key difference vs ESP32-C6, which adds Wi-Fi 6 ( |
consumption_3_3_v_25_c_datasheet_table_5_6_5_9 | — | TX 36 mA @ 0 dBm / 140 mA @ +20 dBm; RX 24–25 mA; modem-sleep 3–17 mA typ; light-sleep 25–85 µA typ; deep-sleep 7 µA typ; power-off 1 µA. |