🛠 Chaîne d'alimentation VDD_IO : tension par banque, eMMC en 1,8 V et rampe

Objectives

Design the power supply for a carrier board for the CM1. Each GPIO bank has its own VDD_IO pin that sets its logic level: 1.8 V, 2.7 V, or 3.3 V, selected per bank — so you can interface 1.8 V on one bank and 3.3 V on another. Note: the eMMC interface is internally fixed at 1.8 V, independently of the VDD_IO settings. The VBAT input must provide at least 2 W to the board. Finally, the power rail ramp-up sequence must follow a descending order (higher voltages rise first); a ramp-up in ascending order exposes the SoC to latch-up. This tutorial documents the complete chain and its verification with an oscilloscope.

Equipment

• A Compute Module 1 on a carrier board or modified IO Board
• Programmable laboratory power supplies (1.8 / 2.7 / 3.3 V rails) for characterization
• Multi-channel oscilloscope for the ramp-up sequence

Complete code

# Chaîne type (carte maison)
VBUS 5V -> régulateur 3.3V (VDD_CORE + VDD_IO banque B)
        -> régulateur 1.8V (VDD_IO banque C + exigences eMMC internes)
VBAT >= 2W en entrée principale (5V selon conception)

# Règles de conception
- VDD_IO : 1.8V / 2.7V / 3.3V PAR BANQUE (broches dédiées par banque)
- eMMC : fixée en interne à 1.8V -> ne jamais y appliquer 3.3V
- Rampe d'ordre DÉCROISSANT : 3.3V puis 2.7V puis 1.8V
  (une rampe croissante risque le latch-up)

# Vérification scope : mesurer t(3.3V stable) < t(1.8V stable)

Expected verification

On the oscilloscope, the 3.3 V rail reaches its plateau before the 1.8 V rail starts rising (descending order respected). Each GPIO bank exhibits the logic levels of its VDD_IO (measurement of high levels on an oscilloscope: ~1.8 V or ~3.3 V depending on the bank tested). The eMMC is read/written normally since its interface remains at the internal 1.8 V. The module draws its power within the minimum 2 W envelope of VBAT without collapse during CPU peaks.

Common errors

• Applying 3.3 V to a line of the eMMC bank thinking that VDD_IO controls it: the eMMC interface is fixed at 1.8 V, damaging the module.
• Ramping up the rails in ascending order (1.8 V first): documented latch-up scenario, the SoC can be destroyed upon power-up.
• Neglecting the 2 W requirement for VBAT: brownout as soon as the CPU and eMMC work together, causing phantom reboots.
• Mixing 1.8 V peripherals on a bank powered at 3.3 V without a level-shifter: input exceeds the absolute maximum rating of the external component.
• Forgetting that each bank has its own VDD_IO: using a single voltage everywhere limits the design and masks level errors.