🛠 Getting Started with Sapphire RV64 SoC on Efinix FPGA

Objectives

This tutorial aims to initialize the Sapphire RV64 SoC based on VexiiRiscv on an Efinix FPGA (Titanium/Topaz/Trion series). The goal is to validate the compilation chain, synthesis under Efinity, and bitstream loading to obtain a functional 64-bit RISC-V core. We will focus on minimal configuration for a stable boot, leveraging advanced capabilities like memory management and debug interfaces.

Required Hardware

• Efinix FPGA: T20 or higher (Titanium, Topaz, or Trion).
• Development board with power supply and JTAG connectors.
• PC with Efinity 2026.1 or later installed.
• USB-JTAG cable or compatible Efinix programming interface.
• Serial terminal (UART) for console output.

Steps

Open Efinity and create a new project selecting the appropriate target FPGA. Import the Sapphire RV64 SoC source files. Ensure physical constraints (.pin) match your board.

1. Efinity Project Configuration

In the SoC configuration file, enable the VexiiRiscv core. Configure the 7-stage pipeline and enable RV64IMACFD_Zba_Zbc_Zbs extensions. If planning Linux support, enable the SV39 MMU. Set the target frequency to 400 MHz (max) to start, or reduce to 100 MHz to validate routing.

1. VexiiRiscv Core Configuration

Enable on-chip RAM (start with 64 KB for bootloader). Configure the external memory controller. For first test, use HyperRAM (500 Mbps) if available, otherwise configure DDR3. Verify memory timings in constraints.

1. Memory Configuration

Launch logical synthesis. Monitor timing reports to ensure critical path meets target frequency. In case of violation, reduce frequency or optimize routing. Once synthesis succeeds, launch physical implementation.

1. Synthesis and Implementation

Generate the final .bit or .hex file. This step converts logical design into FPGA-specific configuration.

1. Bitstream Generation

Connect board to PC via JTAG. Use Efinity programming tool to load bitstream onto FPGA. Once programmed, Sapphire RV64 core boots automatically if bootloader is pre-loaded in ROM or RAM.

1. Programming and Launch

Verification

Open serial terminal connected to configured UART. You should see boot messages or shell prompt. Use standard RISC-V debugger to verify program counter (PC) advances. Place hardware breakpoint (up to 4 available) to inspect register state. Stable frequency of 400 MHz (or configured value) must be confirmed via cycle counter.

Further Reading

Once core is functional, explore multi-core configuration (up to 4 cores). Configure shared L2 cache (64-512 KB) to improve memory performance. Integrate DDR3/LPDDR4x support for heavy applications. Finally, compile RV64-compatible Linux kernel with SV39 MMU enabled for complete operating systems.