🛠 Getting Started with Sapphire RV64 on Efinix FPGA

Objectives

This tutorial aims to initialize the Sapphire RV64 soft-core SoC on an Efinix FPGA (Titanium, Topaz, or Trion T20+ series). You will learn to configure the VexiiRiscv core, generate the bitstream via Efinity, and validate functionality via the UART interface.

Required Hardware

• Efinix FPGA Board (Titanium, Topaz, or Trion T20 or higher).
• Efinity software version 2026.1 or newer.
• USB cable for programming and power.
• Serial terminal (PuTTY, Minicom, or equivalent).

Steps

1. Project Configuration: Launch Efinity and create a new project. Select the target FPGA component matching your board. Ensure the Efinity version is >= 2026.1.
2. Core Integration: Add the Sapphire RV64 IP to your project. In the configuration, select the VexiiRiscv core. For this first test, configure 1 core at 400 MHz with RV64IMACFD extensions enabled. Enable 512 KB on-chip RAM for firmware storage.
3. Peripherals: Configure at least one UART interface (115200 baud) and a JTAG interface for debugging. If your board has DDR3 or LPDDR4x, you can enable it, but internal RAM is sufficient for the initial test.
4. Synthesis and Implementation: Generate the bitstream. Monitor timing reports to ensure the 7-stage pipeline meets the 400 MHz frequency without violations.
5. Programming: Load the bitstream onto the FPGA via the USB cable.
6. Serial Connection: Open a serial terminal on the COM port associated with the configured UART. Reset the board to start the boot process.

Verification

You should see the bootloader welcome message displayed in the serial terminal. Use the hardware breakpoints (up to 4 available) via the JTAG interface to suspend execution and inspect the RISC-V core registers, confirming that the pipeline is functioning correctly.