🛠 Programmer le cœur LP : le coprocesseur qui ne dort jamais

Expert tutorial: leveraging the C6 low-power coprocessor. In addition to the main 160 MHz RISC-V RV32IMAC core (496.66 CoreMark), the chip embeds a 32-bit LP RV32IMAC core with a two-stage pipeline, up to 20 MHz, which remains powered during deep-sleep along with its 16 KB of LP SRAM and dedicated LP peripherals (LP UART and LP I2C). Use case: a sensor continuously polled by the LP core while the HP core, the radio, and most of the 512 KB of HP SRAM are powered off — the node that only wakes up on an event. Tools: esp-lp-hal from the esp-rs project (esp-hal supports the C6, target riscv32imac-unknown-none-elf) or the LP examples in ESP-IDF. Total chip memory: 512 KB HP SRAM, 16 KB LP SRAM, 320 KB ROM, 32 KB L1 cache. Complete exercise: the LP core monitors the internal temperature sensor, wakes the HP core when the threshold is exceeded, the HP core enables Wi-Fi in TWT mode, sends a frame, then the entire system drops back to the ~7 µA deep-sleep state. >